home *** CD-ROM | disk | FTP | other *** search
/ Aminet 33 / Aminet 33 - October 1999.iso / Aminet / util / misc / VMM_src.lha / VMM / sv_regs40.asm < prev    next >
Encoding:
Assembly Source File  |  1995-12-16  |  13.5 KB  |  401 lines
  1.                INCLUDE   "exec/funcdef.i"
  2.                INCLUDE   "exec/exec_lib.i"
  3.                INCLUDE   "macros.i"
  4.                INCLUDE   "shared_defs.i"
  5.  
  6. * $Id: sv_regs40.asm,v 3.6 95/12/16 18:36:07 Martin_Apel Exp $
  7.  
  8.                XDEF      _ReadVBR
  9.                XDEF      _CPushP40
  10.                XDEF      _CPushL40
  11.                XDEF      _PFlushP40
  12.                XDEF      _PFlushA40
  13.                XDEF      _SetMMUState40
  14.                XDEF      _ReadMMUState40
  15.                XDEF      _SaveMMUState40
  16.                XDEF      _RestoreMMUState40
  17.                XDEF      _GetPageSize40
  18.  
  19.                XDEF      _GenDescr40
  20.                XDEF      _EmptyFunc
  21.  
  22.                MACHINE   68040
  23.  
  24.  
  25.                SECTION   CODE
  26.  
  27. _ReadVBR:      movem.l   a5/a6,-(sp)
  28.                lea       ReadVBR(pc),a5
  29.                move.l    $4,a6
  30.                jsr       _LVOSupervisor(a6)
  31.                movem.l   (sp)+,a5/a6
  32.                rts
  33.  
  34. ReadVBR:       movec     VBR,d0
  35.                rte
  36.  
  37. **************************************
  38.  
  39.                ALIGN_LONG
  40. _CPushP40:     movem.l   a5/a6,-(sp)
  41.                move.l    12(sp),a0
  42.                lea       CPushP(pc),a5
  43.                move.l    $4,a6
  44.                jsr       _LVOSupervisor(a6)
  45.                movem.l   (sp)+,a5/a6
  46.                rts
  47.  
  48.                ALIGN_LONG
  49. CPushP:        CPUSHP    BC,(a0)
  50.  
  51.                rte
  52.  
  53. **************************************
  54.  
  55.                ALIGN_LONG
  56. _CPushL40:     movem.l   a5/a6,-(sp)
  57.                move.l    12(sp),a0
  58.                lea       CPushL(pc),a5
  59.                move.l    $4,a6
  60.                jsr       _LVOSupervisor(a6)
  61.                movem.l   (sp)+,a5/a6
  62.                rts
  63.  
  64.                ALIGN_LONG
  65. CPushL:        CPUSHL    BC,(a0)
  66.  
  67.                rte
  68.  
  69. **************************************
  70.  
  71.                ALIGN_LONG
  72. _PFlushP40:    movem.l   a5/a6,-(sp)
  73.                move.l    12(sp),a0
  74.                lea       PFlush_cmd(pc),a5
  75.                move.l    $4,a6
  76.                jsr       _LVOSupervisor(a6)
  77.                movem.l   (sp)+,a5/a6
  78.                rts
  79.  
  80.                ALIGN_LONG
  81. PFlush_cmd:    dc.w      $f508               ; pflush (a0)
  82.                rte
  83.  
  84. **************************************
  85.  
  86. _PFlushA40:    movem.l   a5/a6,-(sp)
  87.                lea       PFlushA_cmd(pc),a5
  88.                move.l    $4,a6
  89.                jsr       _LVOSupervisor(a6)
  90.                movem.l   (sp)+,a5/a6
  91.                rts
  92.  
  93. PFlushA_cmd:   dc.w      $f518               ; pflusha
  94.                rte
  95.  
  96. **************************************
  97.  
  98. _SetMMUState40:
  99.                * Called from C as:
  100.                * void SetMMUState40 (MMUState40*)
  101.  
  102.                movem.l   a5-a6,-(sp)
  103.                move.l    12(sp),a0                   ; start address of MMUState
  104.  
  105.                PRINT_DEB "New URP = %08lx",MS40_URP(a0)
  106.                PRINT_DEB "New SRP = %08lx",MS40_SRP(a0)
  107.                PRINT_DEB "New ITT0 = %08lx",MS40_ITT0(a0)
  108.                PRINT_DEB "New ITT1 = %08lx",MS40_ITT1(a0)
  109.                PRINT_DEB "New DTT0 = %08lx",MS40_DTT0(a0)
  110.                PRINT_DEB "New DTT1 = %08lx",MS40_DTT1(a0)
  111.                IFD       DEBUG
  112.                move.l    MS40_TC(a0),d0
  113.                PRINT_DEB "New TC = %08lx",d0
  114.                ENDC
  115.                
  116.                move.l    4,a6
  117.                lea       SetMMUState40(pc),a5
  118.                jsr       _LVOSupervisor(a6)
  119.                movem.l   (sp)+,a5-a6
  120.                rts
  121.  
  122. SetMMUState40: suba.l    a1,a1
  123.                movec     a1,TC                       ; disable MMU, assumes
  124.                                                      ; direct mapping of RAM
  125.                                                      ; address
  126.                move.l    MS40_URP(a0),d0
  127.                movec     d0,URP
  128.                move.l    MS40_SRP(a0),d0
  129.                movec     d0,SRP
  130.                move.l    MS40_ITT0(a0),d0
  131.                movec     d0,ITT0
  132.                move.l    MS40_ITT1(a0),d0
  133.                movec     d0,ITT1
  134.                move.l    MS40_DTT0(a0),d0
  135.                movec     d0,DTT0
  136.                move.l    MS40_DTT1(a0),d0
  137.                movec     d0,DTT1
  138.                move.l    MS40_TC(a0),d0
  139.                dc.w      $f518                       ; pflusha
  140.                movec     d0,TC                       ; set TC to desired state
  141.                rte
  142.  
  143. **************************************
  144.  
  145. _ReadMMUState40:
  146.                * Called from C as:
  147.                * void ReadMMUState40 (MMUState40*)
  148.  
  149.                movem.l   a5-a6,-(sp)
  150.                move.l    12(sp),a0                   ; start address of MMUState
  151.                move.l    4,a6
  152.                lea       ReadMMUState40(pc),a5
  153.                jsr       _LVOSupervisor(a6)
  154.                movem.l   (sp)+,a5-a6
  155.                rts
  156.  
  157. ReadMMUState40: 
  158.                movec     URP,d0
  159.                PRINT_DEB "Old URP = %08lx",d0
  160.                move.l    d0,MS40_URP(a0)
  161.                movec     SRP,d0
  162.                PRINT_DEB "Old SRP = %08lx",d0
  163.                move.l    d0,MS40_SRP(a0)
  164.                movec     ITT0,d0
  165.                PRINT_DEB "Old ITT0 = %08lx",d0
  166.                move.l    d0,MS40_ITT0(a0)
  167.                movec     ITT1,d0
  168.                PRINT_DEB "Old ITT1 = %08lx",d0
  169.                move.l    d0,MS40_ITT1(a0)
  170.                movec     DTT0,d0
  171.                PRINT_DEB "Old DTT0 = %08lx",d0
  172.                move.l    d0,MS40_DTT0(a0)
  173.                movec     DTT1,d0
  174.                PRINT_DEB "Old DTT1 = %08lx",d0
  175.                move.l    d0,MS40_DTT1(a0)
  176.                moveq     #0,d0
  177.                movec     TC,d0
  178.                PRINT_DEB "Old TC = %08lx",d0
  179.                move.l    d0,MS40_TC(a0)
  180.                rte
  181.  
  182. **************************************
  183.  
  184. _SaveMMUState40:
  185.                * Saves the current MMU registers into a private buffer.
  186.                * No inputs, no outputs
  187.                lea       PrivateMMUState,a0
  188.                move.l    a0,-(sp)
  189.                bsr       _ReadMMUState40
  190.                addq      #4,sp
  191.                move.w    #1,MMUStateValid
  192.                rts
  193.  
  194. **************************************
  195.  
  196. _RestoreMMUState40:
  197.                * Restore the MMU registers from the private buffer.
  198.                * No inputs, no outputs
  199.                tst.w     MMUStateValid
  200.                beq       Ready
  201.                lea       PrivateMMUState,a0
  202.                move.l    a0,-(sp)
  203.                bsr       _SetMMUState40
  204.                addq      #4,sp
  205. Ready          rts
  206.  
  207. **************************************
  208.  
  209. GetMMURegs:    * Returns TC   in d3
  210.                *         URP  in d4
  211.                *         DTT0 in d5
  212.                *         DTT1 in d6
  213.                * Does not modify any other registers
  214.  
  215.                movem.l   a5-a6,-(sp)
  216.                move.l    4,a6
  217.                lea       ReadMMURegs(pc),a5
  218.                jsr       _LVOSupervisor(a6)
  219.                movem.l   (sp)+,a5-a6
  220.                rts
  221.  
  222. ReadMMURegs:   moveq     #0,d3          ; on the 68040 TC is only 16 bit
  223.                movec     TC,d3
  224.                movec     URP,d4
  225.                movec     DTT0,d5
  226.                movec     DTT1,d6
  227.                rte
  228.  
  229. ******************************************************************************
  230.  
  231.                BITDEF    TC,E,15        ; TC: Enable 
  232.                BITDEF    TT,E,15        ; TT: Enable
  233.  
  234. _GenDescr40:   * This function generates an MMU page descriptor for
  235.                * a given logical address. It includes all the standard
  236.                * information a page descriptor contains. In addition
  237.                * the U bit is misused to detect a transparent translation
  238.                * register hit. This way there is no need for separate 
  239.                * handling of cache modes and such for each processor
  240.                * type.
  241.                * C prototype:
  242.                *  ULONG GenDescr (ULONG LogAddr);
  243.  
  244.                move.l    4(sp),a0
  245.                movem.l   d2-d6,-(sp)
  246.                bsr       GetMMURegs
  247.                PRINT_DEB "GenDescr40 called for address %08lx",a0
  248.                btst.l    #TTB_E,d5
  249.                beq       DTT0_Disabled
  250.                
  251.                PRINT_DEB "GenDescr40: DTT0 enabled"
  252.                move.l    a0,d0                    ; save address for eor
  253.                move.l    d5,d1                    ; save DTT0 for mask
  254.                move.l    d5,d2                    ; save DTT0 for CM and WP
  255.                eor.l     d5,d0                    ; cmp with DTT0
  256.                asl.l     #8,d1                    ; shift mask
  257.                not.l     d1
  258.                and.l     d1,d0                    ; only look at non-masked bits
  259.                and.l     #$ff000000,d0            ; only A31 - A24 valid here
  260.                bne       NotTT0Hit
  261.  
  262. GenDescrFromTT:
  263.                * a0: logical address
  264.                * d2: contents of appropriate DTTx
  265.  
  266.                PRINT_DEB "GenDescr40: Address matches DTTx"
  267.                and.w     #$64,d2                  ; CM and WP
  268.                move.l    a0,d0
  269.                and.w     #~(PAGESIZE-1),d0
  270.                or.w      d2,d0                    ; put CM and WP into descr
  271.                or.w      #$9,d0                   ; mark as resident and TT hit
  272.                PRINT_DEB "GenDescr40: Returns %08lx from TTx",d0
  273.                movem.l   (sp)+,d2-d6
  274.                rts
  275.  
  276. NotTT0Hit
  277. DTT0_Disabled:
  278.                btst.l    #TTB_E,d6
  279.                beq       DTT1_Disabled
  280.                PRINT_DEB "GenDescr40: DTT1 enabled"
  281.                move.l    a0,d0                    ; save address for eor
  282.                move.l    d6,d1                    ; save DTT1 for mask
  283.                move.l    d6,d2                    ; save DTT1 for CM and WP
  284.                eor.l     d6,d0                    ; cmp with DTT1
  285.                asl.l     #8,d1                    ; shift mask
  286.                not.l     d1
  287.                and.l     d1,d0                    ; only look at non-masked bits
  288.                and.l     #$ff000000,d0            ; only A31 - A24 valid here
  289.                beq       GenDescrFromTT
  290.                PRINT_DEB "GenDescr40: DTT1 does not match"
  291. DTT1_Disabled:
  292.                PRINT_DEB "GenDescr40: Checking page tables"
  293.                btst.l    #TCB_E,d3                ; Check MMU enabled
  294.                beq       MMUTurnedOff
  295.                PRINT_DEB "GenDescr40: MMU is turned on"
  296.  
  297.                * Work through the page tables
  298.                move.l    d4,a1                    ; URP
  299.                
  300.                move.l    a0,d0               
  301.                ROOTINDEX
  302.                PRINT_DEB "Rootindex is %08lx",d0
  303.                move.l    (a1,d0.w*4),d1
  304.                btst.l    #1,d1
  305.                beq       InvalidTranslation
  306.                and.l     #~(POINTERS_PER_TABLE*4-1),d1
  307.                move.l    d1,a1
  308.                move.l    a0,d0
  309.                POINTERINDEX
  310.                PRINT_DEB "Pointerindex is %08lx",d0
  311.                move.l    (a1,d0.w*4),d1
  312.                btst.l    #1,d1
  313.                beq       InvalidTranslation
  314.                and.l     #~(POINTERS_PER_TABLE*4-1),d1
  315.                move.l    d1,a1
  316.                move.l    a0,d0
  317.                btst.l    #14,d3         ; Test pagesize in TC
  318.                beq       Use4KPages
  319.                moveq     #13,d1
  320.                lsr.l     d1,d0
  321.                and.w     #$1f,d0
  322.                bra       GoOn
  323. Use4KPages
  324.                moveq     #12,d1
  325.                lsr.l     d1,d0
  326.                and.w     #$3f,d0
  327. GoOn
  328.                PRINT_DEB "Pageindex is %08lx",d0
  329.                move.l    (a1,d0.w*4),d1
  330.                btst.l    #0,d1
  331.                bne       PageResident
  332.                btst.l    #1,d1
  333.                beq       InvalidTranslation
  334.  
  335.                * This is an indirect table entry
  336.                PRINT_DEB "Following indirection, Entry = %08lx",d1
  337.                bclr.l    #1,d1
  338.                move.l    d1,a1
  339.                move.l    (a1),d1
  340. PageResident               
  341.                bclr.l    #3,d1                    ; delete used bit to mark it
  342.                                                   ; as not transparently translated
  343.                move.l    d1,d0
  344.                PRINT_DEB "Returning %08lx",d0
  345.                movem.l   (sp)+,d2-d6
  346.                rts
  347.  
  348. InvalidTranslation
  349.                PRINT_DEB "Returning invalid descriptor"
  350.                moveq     #0,d0
  351.                movem.l   (sp)+,d2-d6
  352.                rts
  353.  
  354. MMUTurnedOff:  PRINT_DEB "GenDescr40: MMU turned off"
  355.                move.l    a0,d0
  356.                and.w     #~(PAGESIZE-1),d0
  357.                and.w     #$0320,d3                ; mask DCO and DWO in TC
  358.                lsr.w     #3,d3                    ; shift to same position as 
  359.                                                   ; in page-descriptor
  360.                bset.l    #0,d3                    ; resident
  361.                or.w      d3,d0
  362.                movem.l   (sp)+,d2-d6
  363.                rts
  364.  
  365. ******************************************************************************
  366.  
  367. _GetPageSize40:
  368.                movem.l   a5-a6,-(sp)
  369.                move.l    4,a6
  370.                lea       GetPageSize40(pc),a5
  371.                jsr       _LVOSupervisor(a6)
  372.                movem.l   (sp)+,a5-a6
  373.                btst.l    #15,d1
  374.                bne       MMUIsOn
  375.                moveq     #0,d0
  376.                rts
  377. MMUIsOn        move.l    #4096,d0
  378.                btst.l    #14,d1
  379.                beq       Pages4K
  380.                add.l     d0,d0
  381. Pages4K        rts
  382.  
  383. GetPageSize40: movec     tc,d1
  384.                rte
  385.                
  386.  
  387. ***********************************************
  388.  
  389. _EmptyFunc     * Used as a dummy for the MMU function variables
  390.                rts
  391.  
  392. ***********************************************
  393.  
  394.                DSEG
  395.  
  396. MMUStateValid  dc.w      0
  397. PrivateMMUState:
  398.                ds.b      MS40_SIZE
  399.  
  400.                end
  401.